The VLSI Archive (cont.):

Xerox PARC/Caltech Collaboration on VLSI systems research

 

Compiled and edited by Lynn Conway, with the assistance of VLSI team members.

Copyright 2008-10, Lynn Conway

[V 12-11-10]  

 

Background and context:

 

In the early 70's, Carver Mead made important contributions to our understanding of the physical limits of MOS scaling (B. Hoeneisen and C. A. Mead, "Fundamental Limitations in Microelectronics-I. MOS Technology," Solid State Electronics 15:819-829, 1972.). Sensing the coming opportunity for exploiting increased circuit density, Mead began teaching a series of MOS-LSI integrated circuit design courses at Caltech, building upon the nMOS circuit design knowledge emerging in the work of Federico Faggin at Intel Corporation.

 

In the mid-to-late '60's, Lynn Conway contributed to high-performance computer architecture, hierarchical multi-level simulation and the "design of the computer design process" at IBM Research and IBM-ACS, developing insights into key parts of the larger puzzle Mead and Conway would go on to solve.  In the early 70's Lynn undertook the design of a compound OCR/FAX system at Xerox PARC.  Becoming frustrated by the difficulty of implementing her architectural visions in off-the-shelf TTL, she became intrigued by the potential of the new MOS-LSI technology.

 

In 1975, DARPA commissioned a study by the Rand Corporation regarding the basic limitations of microelectronic fabrication, leading to publication of the Sutherland-Mead-Everhart 'ARPA Report' in '76. In parallel with that work, Bert Sutherland (Manager of the Systems Sciences Laboratory at Xerox-PARC) and his brother Ivan Sutherland (Chair of Computer Science at Caltech) began exploring how they might join forces to undertake research on questions raised in the report.

 
[For more on the events leading up to the Xerox PARC/Caltech collaboration, see "Background and content for the Mead-Conway work"]
 

           

Bert Sutherland                                   Ivan Sutherland

 
 
The Xerox PARC / Caltech collaboration:
 
TBD - - - Ivan's Sutherland's letter to Bert Sutherland of January 76, in which he proposed - - -
 

In early '76 the Sutherland brothers established a formal collaboration between research teams at PARC (Lynn Conway and Douglas Fairbairn) and Caltech (Carver Mead, Jim Rowson, Dave Johannsen), to explore and develop design methods and tools that would enable complex digital system architectures to be more easily implemented in silicon than in the past.

 

 

           

Lynn Conway                                  Carver Mead

 

 

Some of the issues explored by the Xerox/Caltech teams were those discussed in the Sutherland-Mead-Everhart ARPA report. Others were outlined by Sutherland and Mead in a Scientific American article, "Microelectronics and Computer Science", published later on in 1977.

 

TBD - - - background on the pioneering personal networked computing environment at PARC, and how this was the perfect place to conduct this research - - - background on Bert Sutherland's research management methods for supporting highly-motivated bright people and turning them loose on hard problems - - -

 

At PARC work got underway on the ICARUS LSI layout system (Fairbairn and Rowson) and at Caltech work began on a data-path chip known as "OM" ("our machine") (Dave Johanssen et al). Mead helped stimulate interest among a wider set of researchers at PARC by offering a short-intensive course on MOS LSI circuit design that summer, based in methods then emerging at Intel Corporation (where Mead served as a top-level consultant). The cross-fertilization of knowledge among PARC and Caltech researchers about device physics, MOS circuit design, computer architecture, design tool development and design-process design was exciting indeed, and the overall potential of the teams' collective knowledge soon became apparent to all involved.

 

 

           

Doug Fairbairn                                    Jim Rowson

 

 

In early '77, Conway invented a new form of scalable, dimensionless design rules. The new rules greatly simplified the conceptualization of VLSI circuit layouts and the implementation of workstation CAD tools for manipulating such layouts. Reflecting on the ideas in "Ivan's letter" of early '76 and on lessons learned from the work of Steinmetz, Conway began speculating with Mead about the possible significance of their collective work. Conway had explored the "design of the computer design process" in her earlier work at IBM-ACS in '66-'68, and sensed that a related and even more expansive opportunity was now at hand.

 

Once these possibilities sank in, Mead and Conway quickly set far more ambitious goals for the project, namely the innovation of an overall "structured design methodology" for VLSI systems. Conway theorized that a methodology could be constructed that was as easily learned as TTL design, and that could be used by digital designers in place of TTL design, thus opening up VLSI design to much wider participation.

 

In an incredibly intense period of collaborative work, Mead and Conway formulated the basics of the new design methodology. The methodology cut through and bypassed previously existing complexities at all levels of abstraction, by carefully selecting what was necessary and sufficient for inclusion, and then leaving out all the rest. No longer would chip design need to involve teams of specialists in computer architecture, logic design, circuit design and circuit layout - few of which had any understanding of design outside their own specialties. Instead it would involve "VLSI designers" who, using the new methods, could undertake custom chip design from architecture to layout.

 

Along the way, Conway worked on a series of tutorial overviews of the methods, trying to figure out how to explain to others what she and Carver were up to (see, for example, a partial overview in Conway's "Notes and Diagrams for a Short Tutorial on LSI Systems", of 12 August '77 - - to be scanned and posted soon). The drafts of these tutorials soon triggered the idea and provided a foundation for the textbook to come.

 

In June of '77, Dave Johannsen began rigorously applying the new "Mead-Conway structured design methodology" to the design of the OM2 at Caltech. The OM2 was completed in December '77, yielding many detailed examples of micro-processor subsystem design using the new methods. Mead offered another integrated circuit design course at PARC that summer, with the aim of interesting more PARC researchers in chip design, and included elements of the new methods in that course.

 

Mead and Conway then faced a dilemma: What could they do with these promising, but as yet unproven, new design methods? Writing papers for journals didn't seem like a plausible way to disseminate paradigm-shifting ideas.

 

The die was cast in a Xerox/Caltech team brainstorming meeting at PARC in the early summer of '77. Lynn suggested the idea of writing a book and self-publishing it using the Alto's. She proposed this as a way to capture, disseminate and evolve the new methods - and "test their theory" that the new methods could be widely applied by digital designers. Work began soon after and a draft of the first three chapters ('prepublication version 1') was ready in time for testing in two courses in the fall of '77. By the spring of '78 the first five chapters ('prepublication version 2') were available for testing in more courses.

 

In parallel with development and documentation of the design methodology, work also proceeded on new, improved tools for chip layout and chip implementation (maskmaking and fabrication).

Fairbairn and Rowson completed the development and refinement of ICARUS (see this video demonstration from '78-'79), with the simplified design rules enabling computationally efficient CAD tools to run well on the new personal computer workstations at PARC. Bob Sproull and Dick Lyon began work on development what would become the CIF 2.0 interchange format, which later enabled wide sharing of design files and design tools, especially via the then-new ARPAnet (internet). A number of Caltech/Xerox chip designs from Mead's summer course were implemented in a multiproject chip set in the fall of '77, further building the team's experience in QTA chip prototyping.

 

- - - to be continued - - -

 

All these developments were to find their way into the textbook to come, and become a part of the overall new system of VLSI design and implementation methods.

 

The evolving Mead-Conway VLSI design methodology was documented, tested and refined via a series of self-published drafts of what would become the textbook Introduction to VLSI Systems. The prepublication versions were used in a succession of integrated circuit and system design courses, in order to test and refine the design methods and their exposition in the text.

 

(see "Drafts of the Mead-Conway Textbook, Introduction to VLSI Systems")

 

 

- - - to be continued - - - by summarizing and linking to the later parts of the Main Links page - - -

 

 

 

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