A Guide to LSI Implementation

Second Edition


Robert W. Hon and Carlo H. Sequin (Editors)


SSL-79-7 January 1980

Copyright 1980 by R. W. Hon and C. H. Sequin. All Rights Reserved







3333 Coyote Hill Road / Palo Alto / California 94304


This page lists the front-matter and detailed contents of "A Guide to LSI Implementation", 2nd Edition  PDF (182p, 7.0mb)

A VLSI Archive Page compiled by Lynn Conway [V 11-15-07].




During the past several years, the LSI Systems Area of Systems Science Laboratory (SSL) at Xerox Palo Alto Research Center (PARC) has conducted research in the architecture and design of integrated systems. One focus of that research, in collaboration with the Caltech Computer Science Department, has been the exploratory development of new design methodologies that simplify integrated system design.

Through this research, new design techniques have evolved and been debugged; these techniques can be more quickly acquired and more widely practiced by system designers than was possible in the past. It has been a period of discovery and iteration, moved forward by courses taught to university EECS students in which the students undertook LSI design projects as part of their class work. This process has lead to the publication of the textbook Introduction to VLSI Systems [Mead & Conway 1980] describing the new design techniques.

In order to make possible an "acid test" of the evolving design methodologies and of the resulting student designs, a parallel effort has been conducted in SSL to investigate, understand, simplify, and make more efficient the procedures for the implementation of LSI design projects. The term "LSI implementation" is defined here as the series of all tasks involved in going from a set of LSI design files to a set of packaged chips ready for functional testing. Implementation thus involves collecting and merging design files into starting frames, converting the merged files into patterning format, making masks, fabricating wafers, and packaging the resulting chips.

Bob Hon and Carlo Sequin have played leading roles in the SSL LSI implementation activities. They originated many of the new standards and procedures, and then validated these techniques while carrying out the implementation of several multiproject chip sets. These implementation activities have led to the discovery of new techniques that greatly reduce both the overall time for implementation and the cost of implementation per design project. Practical methods have been developed for simplifying the interfacing of design groups with mask making and wafer fabrication firms. A standard design-interchange format (CIF 2.0) has evolved from an early Caltech format and is now in widespread use in the universities and industry. All these and more are the subject of this report.

Bob and Carlo are to be congratulated on the success of these efforts and on the production of this timely and useful report. Only those who were near the action can visualize the imagination required and effort invested to reshape the "Silicon Valley folklore" concerning LSI implementation into a comprehensive, general, compact, and straightforward body of knowledge. Their work has been a key factor enabling the rapid spread of the participation of university students, faculty members, and researchers in the new field of VLSI system design.


Lynn Conway

18 January 1980





The 2nd Edition of A Guide to LSI Implementation is a compendium of information on the realization of LSI system designs. It is our hope that this report will enable a wider group of designers in universities and small systems firms to have their LSI chip designs implemented in an economical and timely way. This document also serves to establish some of the context for future SSL reports on research now underway concerning implementation systems for the remote-entry, fast-turnaround implementation of large numbers of VLSI designs.

The first edition of A Guide to LSI Implementation was hastily written in the summer of 1978 by a combination of PARC researchers, consultants and summer student employees. Among those contributing material were Wayne Wilner, Dick Lyon, and Rick Davies (PARC), Maureen Stone (Xerox-ASD), Bob Baldwin (MIT), Peter Dobrowolski (U.C. Berkeley) and Steve Trimberger (Caltech). Lynn Conway, Carver Mead and Doug Fairbairn each spent hours carefully reviewing drafts and offering suggestions. The eleventh hour efforts of all of these people allowed us to finish the first edition in time for Lynn's fall 1978 MIT VLSI design course.

In the year since that course we have had time to evaluate the strengths and especially the shortcomings of the first edition. In reorganizing and trimming it of irrelevant information, we hope to have improved the readability and utility of the work. New material has been added. The availability of electron-beam mask manufacturing facilities has made 5-day mask turnaround possible; we have included information to allow chip implementors to take advantage of this service. Largely through the efforts of Bob Sproull (CMU) and Dick Lyon (PARC), we have been able to address the many questions that have arisen about CIF 2.0. Chapter 7 is now a complete description of CIF 2.0 and serves as the official reference document. A new section has been contributed by MIT graduate student Jim Cherry sharing his experience from the successful 1978 MIT course. This edition has been further improved by input from SSL researchers Martin Newell and Alan Bell.

Xerox Corporation, Carnegie-Mellon University and the Advanced Research Projects Agency of the Department of Defense have been generous in their support of this work. Terri Doughty handled administration, editting, and much of the figure preparation. We are especially grateful to Dick Lyon, who helped us with sound advice and worked many hours solving the less than interesting problems of putting a report of this size together. He and Joe Maleson are responsible for the color plates. Finally, special thanks go to Lynn Conway for her enthusiastic support and encouragement of our work.


Bob Hon


Palo Alto, California

18 January 1980




Table of Contents



Foreward                                                                                                                                             ii

Preface                                                                                                                                                iii

1.     Introduction                                                                                                                               1

2.     IC Design Tools                                                                                         4

2.1   Entering Your Design                                                                                     5

2.2   Hardcopy Output                                                                                         6

2.3   High-Level Descriptions                                                                                 6

2.4   Design Rule Checking                                                                                    8

2.5 Checking for Other Errors                                                                         10

2.6   Simulation as an IC Design Tool                                                                      11

2.7   Designing for Testability                                                                                 17

3.     Silicon Patterning                                                                                      20

3.1   An Introduction to Photolithography                                                                 20

3.2   Mask Generation                                                                                        21

3.2.1 Optically Generated Masters                                                             21

3.2.2 E-Beam Masters                                                                           22

3.2.3 Working Plates                                                                              23

3.2.4 Mask Specification                                                                         25

3.3   Wafer Fabrication                                                                                       27

3.3.1 The Si-Gate NMOS Process                                                           28

4.     Practical Considerations in IC Pattern Preparation                                        31

4.1   Merging Many Projects                                                                                31

4.2   Physical Constraints                                                                                     33

4.3   The Starting Frame                                                                                      33

5.     When the Wafers Are Delivered...                                                              39

5.1   Process Testing                                                                                           39

5.2   Wafer Separation                                                                                        40

5. 3  Chip Packaging                                                                                           41

5.4   Functional Testing                                                                                        42

5.5   Simple Test Systems                                                                                                                 44

5.6   A Concluding Remark                                                                                  48

6.   An Example Starting Frame and Project Chip                                                 50

6.1 The PARC Starting Frame                                                                                               50

6.2 Test Patterns                                                                                                                           56

6.3 Example Project: A Transformational Memory Array                                           64

7.   A CIF Primer                                                                                                                       79

7.1 Definition of CIF 2.0                                                                                                           81

      7.1.1 Syntax                                                                                                                           81

      7.1.2 Semantics                                                                                                                    83

   Non-geometric Commands                                                  83

   Geometric Primitives                                                           85

   Symbols                                                                                90

   Symbol _Interpretation Rules                                               92

      7.1.3 The Relationship Between CIF and Fabricated Chips                              94

      7.1.4 Common Conventions for Using CIF                                                              95

      7.1.5 Future Plans for CIF                                                                                                                                             101

7.2 Ways to Generate CIF                                                                                                                                                       1 02

      7.2.1 Keyboard Interface                                                                                                                                                102

      7.2.2 Programming Languages                                                                                                                                  103

      7.2.3 Interactive Graphical Layout Systems                                                                                           103

      7.2.4 Standard-cell and Gate-array Systems                                                                                        104

      7.2.5 Silicon Compilers                                                                                                                                                      104

7.3 Processing CIF Files                                                                                                                                                               105

      7.3.1 CIF Implementation Guidelines                                                                                                              105

   Parser                                                                                  105

   Interpreter                                                                            108

   Output                                                                                 111

      7.3.2 A Program for Processing CIF                                                                                                               114

   Parser                                                                                  118

   Interpreter                                                                           119

   Output                                                                                  121

7.4 A Final Note                                                                                                                                                                                      122


A.   Optical and E-Beam Mask Specifications                                                                124

B.   Index of Manufacturers                                                                                                                                                      132

C.   Mann 3000 Pattern Generator Format                                                                                                        133

D.   A Basic Library of Symbol Layouts                                                                                                                 137

E.   Additional References                                                                                                                                                          157






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