AG-2
KathailMIT Designers: Vinod Kathail, Keshav PingoliMPC79 Designers and Their Projects
A VLSI Archive Page compiled by Lynn Conway
[V 12-06-07]
Historical background:
Following the success of her M.I.T '78 VLSI design course, Lynn Conway sought ways to dramatically scale up internet access to quick-turnaround chip prototyping, in order to enable wider testing, refinement and evaluation of the new Mead-Conway design methods. In the spring of 1979 she conceived of a new type of internet-based implementation infrastructure for this purpose, and announced its availability to students taking Mead-Conway courses in the fall of '79.
In a crash-effort that summer at PARC, Alan Bell and Martin Newell created a software prototype of the new "MPC System". Lynn's team used the new system to support rapid prototyping of student design projects at many universities that fall, in a large-scale experimental demonstration-trial of the new VLSI design and implementation methods called "MPC79". MPC79 played a vital role in the rapid evolution and validation of the Mead-Conway design methods, and the rapid propagation of the methods into over 100 universities and scores of startup companies within just several years.
Participating Universities and Designers:
The user community for MPC79 was composed primarily of EE/CS students taking the courses in VLSI system design at major universities throughout the United States along with a number of university faculty and research staff members undertaking major VLSI system designs.
The MPC79 chip set contains a total of 82 VLSI system design projects from a total of 124 participating designers. Designs were included from VLSI design courses at M.I.T., Caltech, Stanford University, Univ. of Illinois, and Univ. of Rochester. MPC79 also includes a number of designs by faculty and research staff members at M.I.T., CMU, Stanford, U.C. Berkeley, Univ. of Washington, Yale University, Univ. of Bristol (England), and Univ. of Colorado (Colorado Springs).
This was an amazing set of projects by an amazing group of people, many of whom went on to fame and fortune in high-technology - as you'll see if you scan down the list of names below.
Locating project and designer information, and accessing associated chip photos:
The list of projects below was compiled in Section 3 of the original "MPC79 Implementation Documentation" (PDF), along with wafer-maps and die-maps to enable designers to locate their projects within the two wafer types and twelve die-types and chip-photos.
The projects are listed in groups by university, and alphabetically by project ID within each university group. Each project entry includes the wafer/die/position-number code for the project, the project ID, the project designer(s), a short description of the project's function, the project's bounding box dimensions in microns, and the area of the project in square mm. Here are links to the university groupings below:
Once the wafer/die/position-codes have been found for a particular project, they can be used to locate the project in the MPC79 chip photos. This can be done using the wafer maps and die maps in the MPC79 Chip Photos page, and the links to the photos from that page. High resolution JPGs of each die-type can also be accessed via links in the VLSI Archive Spreadsheet.
CALTECH:
[Summary of designs from CalTech, updated 4-Dec-79 23:13:17]
BJ-5 BartonCT Designer: Eric Barton
Description: LED array driver
Reserved space = 2126 x 2126 microns, Area = 4.52 sq mm
BJ-8 BozzutoCT Designer: Rick Bozzuto
Description: Pulse width to binary converter
Reserved space = 2120 x 1288 microns, Area = 2.73 sq mm
BJ-1 CampbellCT Designer: James Campbell
Description: Logical processing unit with internal registers
Reserved space = 1856 x 1704 microns, Area = 3.16 sq mm
BJ-6 CocconiCT Designer: Alan Cocconi
Description: Array processor
Reserved space = 1896 x 1074 microns, Area = 2.04 sq mm
BL-7 DerbyCT Designer: Howard Derby
Description: Associative Memory
Reserved space = 2170 x 2566 microns, Area = 5.57 sq mm
BL-2 EatonCT Designer: Steve Eaton
Description: Counter/adder
Reserved space = 2500 x 1376 microns, Area = 3.44 sq mm
BM-6 EllisCT Designer: Mike Fills
Description: Stepping motor controller
Reserved space = 2000 x 2500 microns, Area = 5.00 sq mm
BJ-2 FuCT Designer: Sai Wai Fu
Description: Square root generator
Reserved space = 1750 x 1626 microns, Area = 2.85 sq mm
BL-5 GrayCT Designer: Moshe Gray
Description: Array processor
Reserved space = 2534 x 2082 microns, Area = 5.23 sq mm
BL-1 HellerCT Designer: Jack Heller
Description: Digital filter
Reserved space = 2708 x 1326 microns, Area 3.59 sq mm
BJ-10 HoCT Designer: Kuo Ting Ho
Description: 10 bit rate multipler
Reserved space = 2120 x 1110 microns, Area = 2.35 sq mm
BJ-9 KingsleyCT Designer Chris Kingsley
Description: Serial Multipler
Reserved space = 2200 x 2064 microns, Area = 4.54 sq mm
BJ-4 LiCT Designer: Peggy Pey-Yun Li
Description: Two's-complement pipeline multiplier
Reserved space = 2176 x 1326 microns, Area = 2.89 sq mm
BM-1 LigockiCT Designer: Terry Ligocki
Description: Scan converter chip
Reserved space = 2000 x 4108 microns, Area = 8.22 sq mm
BL-4 MostellerCT Designers: Rick Mosteller, Greg Eflan, Dick Lang
Description: Stack-oriented micrprocessor
Reserved space = 4300 x 2996 microns, Area = 12.88 sq mm
BJ-3 PapachCT Designer: A.C. Papachristidis
Description: Magnitude comparator
Reserved space = 2000 x 1126 microns, Area = 2.25 sq mm
BL-8 PedersenCT Designer: Bruce Pedersen
Description: Asynchronous FIFO
Reserved space = 1896 x 2000 microns, Area = 3.79 sq mm
BL-6 PinesCT Designer: Elliot Pines
Description: Expandable clocking pattern generator chip
Reserved space = 1780 x 1780 microns, Area = 3.17 sq mm
BJ-7 PursifulICT Designer: Ralph Puisiful
Description: Self-Timed Queue
Reserved space = 1590 x 1590 microns, Area = 2.53 sq mm
BM-5 RumphCT Designer: David Rumph
Description: DMA controller
Reserved space = 2442 x 2242 microns, Area = 5.47 sq mm
BJ-12 TannerCT Designers: John Tanner and Richard Segal
Description: Single wire interface for a Manipulator (SWIM)
Reserved space = 2000 x 3000 microns, Area = 6.00 sq nun
AG-1 WalpCT Designer: Pat Walp
Description: Array processor
Reserved space = 2126 x 2050 microns, Area = 4.36 sq mm
BL-3 WatteyneCT Designers: Thierry Watteyne and Martine Savalle
Description: BCD/binary comparator
Reserved space = 2100 x 1600 microns, Area = 3.36 sq mm
BJ-11 WhitneyCT Designer: Telle Whitney
Description: Address translator
Reserved space = 1940 x 2126 microns, Area = 4.12 sq mm
[Summary of designs from CMU, updated 4-Dec-79 23:13:17]
AE-5 EbelingCMU Designer: Carl Ebeling
Description: Rebound Sorter
Reserved space = 1856 x 1856 microns, Area = 3.44 sq mm
AE-1 GuptaCMU Designer: Satish Gupta
Description: Video Buffer
Reserved space = 1006 x 5668 microns, Area = 5.70 sq mm
AE-8 HoeyCMU Designer: Dan Hoey
Description: Experimental Adder
Reserved space = 1188 x 1976 microns, Area = 2.35 sq mm
AE-6 KungCMU Designers: H. T. Kung, S. W. Song
Description: Image Processing Chip
Reserved space = 4160 x 2948 microns, Area = 12.26 sq mm
AE-7 SongCMU Designer: Siang W Song
Description: A small database machine
Reserved space = 2224 x 1954 microns, Area = 4.35 sq mm
[Summary of designs from MIT, updated 4-Dec-79 23:13:17]
AB-8 AllenMIT Designers: Don Allen, Jerry Burchfiel
Description: Variable Length Field Decoder
Reserved space = 2218 x 2484 microns, Area = 5.51 sq mm
AB-1 BataliMIT Designer: John Batali
Description: Zero-Crossing Detector for Image Processing
Reserved space = 2644 x 1738 microns, Area = 4.60 sq mm
AC-4 ChuMIT Designers: Tam-Anh Chu, Nhi-Anh Chu, Steve McCormick
Description: Second order digital filter stage
Reserved space = 6146 x 2278 microns, Area = 14.00 sq mm
AB-3 FichtenbaumMIT Designer: Matt Fichtenbaum
Description: A digital pulse rate monitor
Reserved space = 2500 x 2500 microns, Area = 6.25 sq mm
AG-5 GoddeauMIT Designers: David Goddeau, Jonathan Sieber, Chris Terman
Description: A first-in, priority-out buffer
Reserved space = 2928 x 2954 microns, Area = 8.65 sq mm
AB-5 GoodrichMIT Designer: Earl Goodrich
Description: CRT controller
Reserved space = 1856 x 1520 microns, Area = 2.82 sq mm
AB-2 GramlichMIT Designers: Wayne Gramlich, Carl Seaquist
Description: A writable PLA in which the programming
of the AND and OR planes is defmed by contents of static
RAM cells. Also can program feedback loops to form
finite state machines.
Reserved space = 1524 x 1906 microns, Area = 2.90 sq mm
AB-6 GrondalskiMIT Designer: Robert Grondalski
Description: Writeable PLA
Reserved space = 2200 x 2200 microns, Area = 4.84 sq mm
AC-1 HamiltonMIT Designer: Brian Hamilton
Description: Digital Alarm Clock
Reserved space = 2500 x 2500 microns, Area = 6.25 sq mm
AG-2
KathailMIT Designers: Vinod Kathail, Keshav Pingoli
Description: an interpreter for mapping programs onto
a data flow computer
Reserved space = 1590 x 2228 microns, Area = 3.54 sq mm
AB-4
KhouryMIT Designer: John Khoury
Description: Up-Down counter with programmable modulus
Reserved space = 2000 x 1726 microns, Area = 3.45 sq mm
AC-2 PasemanMIT Designer: Bill Paseman
Description: Music Synthesizer
Reserved space = 4126 x 2842 microns, Area = 11.73 sq mm
AB-7 PicardMIT Designer: Len Picard
Description: Variable format field extractor and compactor
Reserved space 2000 x 1688 microns, Area = 3.38 sq mm
AG-3 RivestMIT Designers: Ron Rivest, Len Adleman, Adi Shamir
Description: Section of a Multiplier
Reserved space = 2250 x 2250 microns, Area = 5.06 sq mm
[Summary of designs from Stanford University, updated 4Dec-79 23:13:17]
BI-6 AtlasSU Designers: Les Atlas, Doug Galbraith
Description: This project is an neural-stim. interval timer
Reserved space = 2478 x 1378 microns, Area = 3.41 sq mm
BK-4 BaskettSU Designer: Forest Baskett
Description: This project is an Ethernet synchronizer
Reserved space = 2240 x 2720 microns, Area = 6.09 sq mm
BK-7 BechtolsheimSU Designers: Andy Bechtolsheim, Thomas Gross
Description: A parallel search table for log arithmetic
Reserved space = 1514 x 3180 microns, Area = 4.81 sq mm
BK-5
Clark2SU Designer: Jim Clark
Description: This project is a self-timed clock element
Reserved space = 1606 x 1688 microns, Area = 2.71 sq mm
BK-8 ClarkSU Designer: Jim Clark
Description: This project is a simple graphics ALU
Reserved space = 2976 x 2764 microns, Area = 8.23 sq mm
BI-5 ElahianSU Designers: Kamran Elahian, Fred Basham
Description: This project is a UART line speed determiner
Reserved space = 1856 x 1856 microns, Area = 3.44 sq mm
BK-3 FrolikSU Designers: Bill Frolik, Roderick Young
Description: This project is a digital timer
Reserved space = 2120 x 2684 microns, Area = 5.69 sq mm
BI-2 GehlbachSU Designers: Steve Gehlbach, Joe Sharp, Bill Jansen
Description: This project is a fast 16-input adder
Reserved space 3180 x 1856 microns, Area = 5.90 sq mm
BI-8 HannahSU Designers: Peter Eichenberger, Marc Hannah
Description: This project is a rectangle generator
Reserved space = 2386 x 2140 microns, Area = 5.11 sq mm
BI-7 lierndonSU Designers: Matt Hemdon, Jeff Thorson
Description: This project is a typesetting machine
Reserved space = 3170 x 2000 microns, Area = 6.34 sq mm
BI-1 MacomberSU Designers: Scott Macomber, Bob Clark
Description: This project is a parallel/serial multiplier
Reserved space = 2000 x 2000 microns, Area = 4.00 sq mm
BI-3 MarkeeSU Designers: Pat Markee, Irene Watson
Description: This project is a digital clock
Reserved space = 2120 x 1424 microns, Area = 3.02 sq mm
BK-1 MathewsSU Designers: Rob Mathews, John Newkirk
Desciption: This project is the infamous Buffalo chip
Reserved space = 5180 x 1134 microns, Area = 5.87 sq mm
BI-4 NoiceSU Designers: David Noice, Neil Midkiff
Description: This project is a multiplier/divider
Reserved space = 2888 x 1576 microns, Area = 4.55 sq mm
BK-6 OhChinSU Designers: Soo-Young Oh, Dae-Je Chin
Description: An automatic thermostat time controller
Reserved space = 2120 x 1700 microns, Area = 3.60 sq mm
BN-7 TarsiSU Designers: Mike Tarsi, Nagatsugu Yamanouchi
Description: This project is a multifunction digital clock
Reserved space = 2140 x 2276 microns, Area = 4.87 sq mm
BN-6 UttSU Designers: Steve Utt, Shalom Ackelsberg
Description: This project is part of a pancreas prosthesis
Reserved space = 2000 x 2000 microns, Area = 4.00 sq mm
BI-9 WulffSU Designers: Bob Wulff, Tom Bennett
Description: This project is a bit slice of a multiplier
Reserved space .= 2120 x 1856 microns, Area = 3.93 sq mm
BK-2 ZarghanSU Designers: Bahman Zargham, Jerry Huck
Description: This project is a multiplexed communications link
Reserved space = 1590 x 1550 microns, Area = 2.46 sq mm
[Summary of designs from U. C. Berkeley, updated 4-Dec-79 23:13:17]
BM-2 DecuirUCB Designers: J. Decuir, C.H.Sequin
Description: Squareroot of 3 approximator for radix-3 block
in FFT computer
Reserved space = 2650 x 3278 microns, Area = 8.69 sq. mm
BM-3 FungUCB Designers: W.-C. Fung, C.H.Sequin
Description: General purpose barrel shifter for staggered ,
pipelined data in an FFT computer
Reserved space = 2484 x 2650 microns, Area = 6.58 sq mm
BM-4 LandmanUCB Designer: Howard A. Landman
Description: This project is a reprogrammable PLA,
with 8 each inputs, pterms, and (tri-state) outputs.
Reserved space = 2600 x 1590 microns, Area = 4.13 sq
BM-7 SequinUCB Designer: Carlo H. Sequin
Description: Dual 16-stage FIFO with double rail signalling
Reserved space = 2460 x 980 microns, Area = 2.41 sq mm
[Summary of designs from University of Illinois, updated 4-Dec-79 23:13:17]
AD-3
AdrianUI Designers: Frank Adrian, Nick Fiduccia, Bud Pflug
Description: Functional equivalent of AMD 2901 ALU
to compare MOS, TTL
Reserved space = 2710 x 4388 microns, Area = 11.89 sq mm
AE-2
ClassUI Designers: Class
Description: Twos complement 4 x 4 array multiplier
Reserved spare = 1714 x 1498 microns, Area = 2.57 sq mm
AD-2 HanesUI Designers: Larry Hanes, Dave Yen•
Description: Twos complement array divider
Reserved space = 2616 x 2636 microns, Area = 6.90 sq
AD-1 LuhuhayUI Designer: Joe Luhukay
Description: Pipelined multiplier, registers also used for testability
Reserved space = 2572 x 4140 microns, Area = 10.65 sq mm
AD-4 MontoyeUI Designers: Bob Montoye, Al Casavant
Description: Carry lookahead adder (soln. proposed by Gajski and Kung)
Reserved space = 2628 x 2626 microns, Area 6.90 sq mm
[Summary of designs from University of Rochester, updated 4-Dec-79 23:13:17]
BN-3 KedemUR Designers: Gershon Kedem and Michel Denber
Description: Infinite precision multiplier
Reserved space = 2698 x 2786 microns, Area = 7.52 sq mm
BN-2 LyonsUR Designer: Bob Lyons
Description: Programmable Frequency Generator
Reserved space = 2748 x 2276 microns, Area = 6.25 sq mm
BN-4 SohmUR Designers: Larry Sohin, Pat Chan, Bill Notowitz
Description: Digital Phase lock loop
Reserved space = 3610 x 2634 microns, Area = 9.51 sq mm
BN-5 TiloveUR Designers: Bob Tilove, Jarek Rossignac
Description: This is a bit slice coordinate transformer
Reserved space = 1934 x 1326 microns, Area = 2.56 sq mm
BN-1 WatanabeUR Designer: Yuki Watanabe
Description: Sorter slice
Reserved space = 2008 x 2240 microns, Area = 4.50 sq mm
[Summary of designs from Other places, updated 4-Dec-79 23:13:17]
AC-3 GlasserOT Designer: Lance Glasser, MIT, via Univ. of Washington
Description: Modulo-6 counter for dice game
Reserved space = 1486 x 808 microns, Area = 1.20 sq mm
AE-9 KehlOT Designers: Ted Kehl, Ram Rao, Ed Lazowska,
Univ. of Washington, Seattle
Description: Address intercept logic for microcomputer
Reserved space = 1818 x 1782 microns, Area = 3.24 sq mm
AE-3 MurrayOT Designer: John Murray, Univ. of Colorado, Colorado Springs,
via Univ. of Washington
Description: 3-bit identity comparator
Reserved space = 1512 x 1642 microns, Area = 2.48 sq mm
AE-4 RogersOT Designer: Mike Rogers, Univ. of Bristol, Bristol, England,
via Univ. of Washington
Description: Simple 3-bit enciphering/deciphering chip.
Reserved space = 1248 x 1708 microns, Area = 2.13 sq mm
AF1 Schip2 Designers: Gerry Sussman, Jack Holloway, Guy Steele, Alan Bell
MIT-AI Laboratory/Xerox PARC-SSL
Description: Lisp Microprocesser
Reserved space = 5926 x 7548 microns, Area = 44.73 sq mm
AG-4 SnyderOT Designer: Larry Snyder, Yale University,
via University of Washington
Description: A binary tree processor that computes boolean
functions, with inputs at the leaves and output at the root.
Reserved space = 3418 x 3430 microns, Area = 11.72 sq mm
LynnConway.com > VLSI > Lynn Conway's VLSI Archive > MPC79 > MPC79 Implementation Documentation > MPC79 Designers and Their Projects