United States Patent 3,718,912:

 

INSTRUCTION EXECUTION UNIT

Leo J. Hasbrouck, Bill C. Madden, Robert P. Rew, Edward H. Sussenguth, John R. Wierzbicki

 

Filed: Dec. 22, 1970.

Issued: Feb. 27, 1973.

Assignee: International Business Machines Corporation

 

 

Note to readers: Following are parts of the cover sheet, selected text from the "Summary of the Invention", and several figures from this IBM patent. This patent was filed by members of the IBM ACS-360 architecture and engineering groups, some of whom had participated in the IBM ACS-1 project. You'll note that this is an effort to cover parts of the dynamic instruction scheduling invention, including multi-out-of-order issuance of instructions. As is turns out, this patent didn't teach those ideas very clearly or well, perhaps intentionally not doing so as is often the case with patents, and thus wasn't clearly recognized early-on outside IBM for what it was trying to do. However, many later patents on multi-issue DIS do reference this patent, since it was apparantly trying to cover that territory. Curiously, the patent makes no mention of Lynn Conway's earlier invention of DIS, or of the tutorial paper about DIS, from the IBM ACS-1 efforts of '65-'66 (Lynn's former name is not among those listed as inventors on this patent).

 

 

 

 

Text from column 1 of the Summary of the Invention:

 

 

Some key text from Column 2 of the "Summary":

 

 

Figures showing the concept of Source/Destination interlock comparisons in the Contender Stack:

 

 

Hmm. This seems somewhat familiar to those knowing how the ACS-1 machine worked. For a comparison, see the original DIS tutorial paper from the ACS-1 project, and also the ACS-1 Timing Simulator Manual which shows examples of multi-out-of-order instruction-issuance from the contender stacks and the "bubble-up" process of refilling those stacks.