A Guide to LSI Implementation

Robert Hon and Carlo Sequin

SEPTEMBER 27, 1978

Copyright 1978 by Xerox Corporation

 

 

XEROX

PALO ALTO RESEARCH CENTER 3333 Coyote Hill Road

Palo Alto, California 94304

 

 

This page lists the front-matter and detailed contents of "A Guide to LSI Implementation", 1st Edition  PDF (155p, 5.7mb)

A VLSI Archive Page compiled by Lynn Conway [V 5-20-08].

 


 

Table of Contents

Foreword

1.          The New IC Designer                                                                                                    1

2.         IC Design Tools                                                                                                             4

2.1  Automated Design Aids                                                                                                     5

2.2  IC Layout Languages                                                                                                         9

2.3  Checking Your Design                                                                                                     15

2.4  Simulation as an IC Design Tool                                                                                       19

3.       An Overview of IC Implementation                                                                              26

3.1  Mask Generation                                                                                                               26
reticles, masters, submasters, working plates, blowbacks

critical dimensions, parity marks, fiducials, alignment marks

3.2  The Basic Fabrication Process                                                                                           28
Si gate NMOS process

photolithography tradeoffs, processing tradeoffs

4. Nasty Details and IC Pattern Preparation                                                                       32
the starting frame, alignment marks, packaging constraints,

scribe lines, chip size and yielcl test patterns

5.       Mask Specification                                                                                                         38

           implications of current PG machines,

           working plate polarity, mask compensation for processing

6.       When the Wafers Are Delivered...                                                                                 40

6.1  Wafer Separation                                                                                                             40

6.2  Chip Bonding                                                                                                                   41

6.3  IC Testing                                                                                                                        43

7.       An Example Project Chip and Starting Frame                                                               51

7.1  The Starting Frame                                                                                                            51
 
alignment marks, critical dimensions, etch test patterns, scribe lines

7.2  Test Patterns                                                                                                                    58

7.3  An Example Project                                                                                                         63

Appendices

A.       Specifications Sent to the Mask House                                                                             68

B.       Index of Manufacturers                                                                                                    72

C.       Mann 3000 Pattern Generator Format                                                                             74

D.       ICLIC Manual                                                                                                                 79

E.       Basic Library of Symbols                                                                                               100

F.        References                                                                                                                     142


 

 

Foreword

This book was produced as a result of the 1978 Summer Program of the LSI Systems Area of Xerox Palo Alto Research Center (PARC). This program involved the participation of summer employees Bob Baldwin (undergraduate at MIT), Peter Dobrowolski (master's student at UC Berkeley), Bob Hon (Ph.D. student at Carnegie-Mellon University), and Steve Trimberger (Ph.D. student at UC Irvine). These students and our consultants Carlo Sequin (professor at UC Berkeley), Carver Mead (professor at Caltech), and Jim Rowson and Dave Johannsen (Ph.D. students at Caltech) have spent the summer working with us on various aspects of integrated systems design and implementation, including a multi-project chip and this document. Xerox employees who participated in the program include Rick Davies (General Sciences Lab), Maureen Stone (Advanced Systems Department), and our own group members Lynn Conway, Doug Fairbairn, Dick Lyon, and Wayne Wilner.

In spite of the difficulty of working on a short schedule with people of widely differing backgrounds, co-editors Bob Hon and Carlo Sequin have managed to produce this timely document, to help bring integrated system capability to a wide range of users, including universities. Bob Hon, the principal author, has collected considerable relevant information about current patterning and fabrication technologies, and prospects for future changes that readers should be aware of; he also personally carried the PARC summer-1978 multi-project chip from individual project designs through maskmaking, and arranged for subsequent processing.

The other three students cooperated in the writing of this book by contributing sections, and became involved in the multi-project chip by producing project designs and by helping with design tools. Bob Baldwin assisted in establishing a cell library, designing two projects, writing design conversion software, and documenting his work in sections of this book. Steve Trimberger is building our new design system, and has built some of our existing tools: he has provided the writeup on automated design systems, and designed a project with the aid of a hybrid of our graphical layout system and a general purpose programming language. Peter Dobrowolski designed and built some IC test hardware for us this summer, and wrote the book section which summarizes testing strategies: in addition, his chip project illustrates the use of PLA's for a novel bit-staggered timing scheme for fast arithmetic functions.

Rick Davies provided the section on process test patterns, documenting his project on the chip. Maureen Stone wrote a section on symbolic layout languages and the appendix on ICLIC. Within our own group, Wayne Wilner has described the problem of design rule checking, and Dick Lyon has provided the section on circuit simulation.

Carver Mead provided important technical advice and encouragement. Lynn Conway (manager of our LSI Systems Area) provided the drive that it took to make this book happen. She and Carver have recently written the book Introduction to VLSI Systems, which is assumed to be available as a reference with this document.

Richard F. Lyon

Douglas G. Fairbaim

 

The authors would like to acknowledge the help of Dick Lyon, who spent considerable time working on this document as the final deadline approached.

Bob Hon

Carlo Sequin

 


 

1. The New IC Designer

Traditionally the design and development of integrated circuits (IC's) has been the domain of specialists with substantial training in this "art". With the emergence of more powerful computer aids and of reasonably standardized IC processing techniques, IC design can be simplified to the point where it becomes a routine engineering step in the development of a special purpose system. MOS devices are particularly simple and straightforward as long as one stays away from the smallest geometries feasible. With reasonable, relaxed design rules the performance of standard MOS circuit blocks such as inverters, pass gates, buffers, NOR gates and composites of these blocks become as predictable as TTL circuits. Using a structured design approach, such as the one promoted by Mead and Conway in Introduction to VLSI Systems [Mead 1978], it is possible for people with only a minimal understanding of the device physics of a MOS transistor to produce operational integrated circuits of substantial size. Thus, a systems designer can now sit in front of an interactive graphics terminal and produce the layouts of a set of masks for a special purpose integrated circuit. Such personalized IC's can greatly enhance the functionality of the system to be built or alternatively may dramatically reduce the total chip count for a system of given specifications

In such a venture it is often not important to produce an integrated circuit of the highest layout density or of the highest performance, which could only be obtained by pushing the limits of present-day technology. Normally the main concern is to get a properly working chip with the shortest possible turnaround time. It is here that effective design tools and, even more importantly, the proper design methodology, are crucial. These issues are discussed in Introduction to VLSI Systems. The second, equally important part is to get the IC designs implemented. In an environment that is not already set up to produce custom-designed IC's as a routine step, the designer himself often has to be the driving force behind the implementation of the first few IC's. In this situation many months arc often wasted because of unsuitable preparation or unavailability of the necessary information, leading to frustrating delays in the project schedules and to abandoning the custom-made IC approach altogether. These are problems that we hope this document will prevent.

Converting an integrated circuit design into a finished, packaged, and tested chip is more a time consuming task than a difficult one. Dozens of important details have to be observed to prevent disasters or costly delays. Up to this point a concise description of the specific details and necessary steps has not been available. Specific information had to be gathered from scattered sources including personal interviews with "old hands in the trade".

This document is intended to be a guide along the entire path from the design of the layout of the integrated circuit, through mask generation, IC wafer fabrication, and chip packaging to the testing of the finished circuits. Important decision points and potential pitfalls along the way are clearly spelled out.

Often several IC designs will be combined into a single multi-project chip. In this manner the cost of mask generation and wafer fabrication, as well as the organizational overhead involved in pushing the future IC through all critical stages can be shard among a larger group of people. In an academic or research environment this coordination of several experiments into one IC project is particularly important, so that not every student has to worry about all of the details of mask and wafer processing. Certain features such as test patterns to measure device performance, alignment marks, and chip separation lines (scribe lines) can be standardized and re-used in subsequent multi- project chips. Sticking to the same features, similar basic chip formats and established procedures to generate the multi-project chips will help to streamline this process and enhance the chance for satisfactory results. Someone, therefore, will have to act as a coordinator. His or her first task will be to merge the different files describing the various IC designs with the starting frame containing the mentioned standard features. He will then interact with the mask house and the fabrication line, making sure that both places have all the information that they need and that there is no misunderstanding in what they are expected to do. In order to avoid unnecessary delays he should constantly keep track of the state of the project and try to effect smooth interactions between the various parties involved. This includes hand-carrying the magnetic tape with the designs from the research site to the mask house, the set of working plates from the mask house to the fabrication line, finished wafers from the fab line to the dicing and bonding station, and finally a number of packaged chips to the testing area. This document describes the real-life problems and details which the coordinator must be aware of to effectively carry out these tasks. But even the occasional designer of an individual IC should be aware of the overall process, so that he or she may better understand certain implications on their own activity. As with any other system implementation technology, the types of design aids and the methods of fabrication impact the type and quality of design which is done. The most effective systems designers will therefore understand at least the basic aspects of design aids and checking tools as well as mask and wafer fabrication.

Chapters 2 through 6 outline the basic path from IC design to the finished product. Chapters 2, 3 and 6 should be studied even by people who never dream of becoming coordinators of multi- project chips, since they set the stage for proper IC design. For the coordinator chapters 4 and 5 are absolutely vital. Chapter 7 gives an example of a multi-project chip produced at Xerox PARC during the summer of 1978. It carried 10 experiments including a wide range of logic, arithmetic and memory circuits and a test pattern. Appendix A contains a listing of the instructions sent to the mask house concerning this particular chip.

Throughout the text italics are used to introduce vocabulary which the designer should know. No attempt is made to tabulate precise definitions of terms, but enough information can be inferred from the context that the reader can search for more details if necessary. Appendix F provides pointers to in-depth articles and texts covering particular aspects of IC implementation. Integrated circuit manufacturers can often provide valuable information and insight into most phases of IC implementation: Appendix 13 is a listing of some that we have dealt with. It is by no means exhaustive, and the reader should not hesitate to make his own contacts where possible.

 

 

 

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